1. Field of the Invention
The present invention relates to synchronous memory devices, and more particularly, to a synchronous memory device in which data are written to memory cells in response to activation of a write command, and a data write method using the same.
2. Description of the Related Art
At present, for the purpose of improving the access time of memory devices, synchronous memory devices in which operation is synchronized with an external system clock have been developed. In synchronous memory devices, a data write or read operation is controlled based on the external system clock signal. Thus, if the frequency of the system clock signal increases due to an increase in the operating speed of an external system that outputs the clock signal, the operating speed for the data write or read must be increased in response to the frequency increase.
In a general synchronous memory device, a reduced access time to the memory device relative to the system clock frequency during a data read operation can be implemented by increasing column address strobe (CAS) latency. CAS latency is defined as the period of time from the activation of a CAS signal to the output of data. That is, as the operating frequency of an external system increases due to a high operating speed thereof, the data can be output in synchronism with the system clock by increasing the CAS latency.
During the data read operation, although the read operating speed of the synchronous memory device can not increased, data can be output in synchronization with the system clock having an increased frequency, as long as the point in time at which data is read from the point in time at which the CAS signal was generated, that is, the CAS latency, is increased. This is possible because during the data read operation, the address of the succeeding memory cell to be read can be input in advance while the present data is being processed.
However, unlike the data read operation, during the data write operation, the process of writing the present data must be completed before inputting the succeeding data process. However, the data write period of time, i.e., from the activation of a write command to the data writing to the memory cell, is shorter than the system clock cycle, so that one write operation can be completed within the system clock cycle.
However, as the system clock cycle is shortened with the increased operating speed of the system, the data write operation cannot be completed within the system clock cycle. Thus, the maximum operating speed of the system is restricted by the write cycle of the memory device therein.